A phase locked loop circuit includes three essential blocks, namely, a phase/frequency comparator, a charge pump and integrator and a voltage controlled oscillator. The function of the phase locked loop is to adjust the oscillator frequency until it tracks the input signal except that in a phase condition the frequency of the input may be a subharmonic of the oscillator frequency. This frequency may then be used to synchronize the input data. In cases where the incoming data is a self clocking bit stream, the comparator system is used to extract the clock information from the data stream itself.
The purpose of the phase/frequency comparator is to compare the phase and/or frequency of incoming data signals to clock signals in order to establish an oscillator frequency which can synchronize the data signals. Thus, any jitter in the incoming data can be eliminated and the synchronized data can then be fed into an external decoder.
In a typical application there are periods when data is being sent and periods when no data is being sent. External control circuitry is normally used to identify when data is being sent so that proper control circuitry can be established. Before data is sent, a crystal oscillator or a clock generator generating a clock signal of a known or reference frequency sends a the clock signal of a fixed frequency to the system. Accordingly, when data transmission begins the system is in a frequency mode and locked to the reference frequency signal. Immediately prior to data being sent there is a preamble condition of a fixed known frequency that is a sub-harmonic (e.g., 1/2, 1/3, 1/4 . . . ) of the clock frequency.
On arrival of the preamble condition the system is switched from a frequency mode to a phase mode. In the phase mode the phase detector establishes a phase window of -180 degrees to +180 or one clock period of the a voltage controlled oscillator (VCO). The task of the phase detector is to compare the relative phase of each data bit with the phase of a VCO clock bit. Thus, phase comparison is made only in the presence of a data bit utilizing a necessarily well centered phase window. For a detected phase error of zero degrees the phase detector applies no correction to the charge pump. A detected phase error of +180 degrees has a maximum positive correction while a detected error of -180 degrees has a maximum negative correction. In the complete phase-locked loop, if the data bit precedes the voltage controlled oscillator clock bit, i.e. the voltage controlled oscillator clock appears slow or lagging, the sense of the corrective action of the phase detector/charge pump is to increase the frequency of the voltage controlled oscillator; and conversely, if the voltage ,controlled oscillator clock bit precedes the data bit the oscillator the frequency is decreased.
Previous methods of implementing a phase detector have employed one of three techniques to enable the phase detector for phase comparison only when a data bit is present. The first method uses passive tapped delay line with a delay of 1/2 the period of the VCO clock. The phase comparison is made relative to the rising edges of the delayed data bit and the VCO clock. Passive delay lines which are distributed inductors and capacitors are not suitable for semiconductor integration. Consequently, it is undesirable to require an off chip delay line for reasons of expense, space and convenience. A second phase detector approach similar to the above is the use of an active delay in place of the passive one. Although an active delay can be integrated on a chip, it requires more circuitry for the integration and, thus makes the circuit relatively large and expensive.
A third phase detector method eliminates the need for the delay by establishing a variable charge period which occurs due to a data bit and which enables a fixed discharge period lasting approximately half the period of the oscillator. When the two signals are in phase-lock they are approximately 180 degrees out of phase, and the duration of the charge and discharge periods are equal.
An all digital frequency compare method which has previously been used with phase compare method three employs logic gates and digital memory elements (flip flops). It has a phase quadrature lock-up problem in which there are two stable phase relationships which occur with a .+-.90 degree relative phase error. Because this bistable condition is indeterminate and random, randomly occurring disturbances to the phase locked loop can occur when switching the phase mode to frequency mode and back again result. A design approach to the third method has been to use separate circuits for the phase compare and frequency compare modes of operation. The separate circuitry for phase and frequency compare has involved greater complexity and cost than would be the case for a single circuit adapted to carry out both comparison functions. Traditional combined circuits which have been capable of doing both a phase and a frequency comparison such as phase methods one and two have also required a separate compare cycle enable circuit which is activated by the undelayed input for a comparison or which is constantly enabled for a frequency compare mode of operation. Clearly, the more circuitry involved the more will be the delay and the slower will be the operating frequency of the circuit.
Accordingly, an object of the present invention is to provide an improved phase locked loop circuit. A further object of the present invention is to provide a phase-locked loop circuit capable of operating at relatively high frequencies. Yet another object of the present invention is to provide a phase locked loop circuit which eliminates the uncertainty associated with phase quadrature lock up in the frequency mode of operation.